CS501 : Advance Computer Architecture

Course Overview

Course Synopsis

This course will provide the students with an understanding of the various levels of studying computer architecture, with emphasis on instruction set level and register transfer level. This course prepares the students to use basic combinational and sequential building blocks to design larger structures like Arithmetic Logic Units, memory subsystems, I/O subsystems etc.

Course Learning Outcomes

At the end of the course, you should be able to:

  • Understand Instruction Set Architecture design and Central Processing Units of the RISC (Reduced Instruction Set Computers) and the CISC (Complex Instruction Set Computers) type
  • Describe the behavior and structure of a computer using RTL (Register transfer language)
  • Explain Pipelining and instruction level Parallelism
  • Explain the I/O sub systems
  • Understand Magnetic disk drives
  • Explain the memory module of computer
  • Understand Number Systems and Radix Conversion


Course Calendar

TopicLectureResourcePage
Introduction1Handouts5 - 20
Instruction Set Architecture2Handouts21 - 33
Introduction to SRC Processor3Handouts34 - 41
ISA and Instruction Formats4Handouts42 - 56
Description of SRC in RTL5Handouts57 - 66
RTL Using Digital Logic Circuits6Handouts67 - 84
Design Process for ISA of FALCON-A7Handouts85 - 89
ISA of FALCON-A8Handouts90 - 103
Description of FALCON-A and EAGLE using RTL9Handouts104 - 123
FALCON-E and ISA Comparison10Handouts124 - 149
Assignment 1
CISC and RISC11Recommended Book*95 -1 37
CPU Design12Handouts151 - 161
Structural RTL Description of the FALCON-A13Handouts162 - 170
External FALCON-A CPU14Handouts171 - 180
Logic Design and Control Signals Generation in SRC15Handouts181 - 194
Control Unit Design16Handouts195 - 205
Assignment 2
Machine Reset and Machine Exceptions17Handouts206 - 212
Pipelining18Handouts213 - 220
Pipelined SRC19Handouts221 - 227
Hazards in Pipelining20Handouts228 - 233
Quiz 1
Instruction Level Parallelism21Handouts234 - 238
Microprogramming22Handouts239 - 250
Mid Term Examination
I/O Subsystems23Handouts251 - 264
Designing Parallel Input and Output Ports24Handouts265 - 277
Input Output Interface25Handouts278 - 291
Programmed I/O26Handouts292 - 302
Interrupt Driven I/O27Handouts303 - 312
Interrupt Hardware and Software28Handouts282 - 294
Assignment 3
FALSIM29Handouts295 - 309
Interrupt Priority and Nested Interrupts30Handouts310 - 315
Direct Memory Access (DMA)31Handouts349 - 357
Magnetic Disk Drives32Handouts358 - 362
Error Control33Handouts363 - 367
Number Systems and Radix Conversion34Handouts368 - 376
Multiplication and Division of Integers35Handouts377 - 382
GDB
Floating-Point Arithmetic36Handouts383 - 386
Components of memory Systems37Handouts387 - 395
Memory Modules38Handouts396- 398
The Cache39Handouts399 - 407
Virtual Memory40Handouts408 - 415
Quiz 2
Numerical Examples of DRAM and Cache41Handouts416 - 425
Performance of I/O Subsystems42Handouts426 - 431
Networks43Handouts432 - 436
Communication Medium and Network Topologies44Handouts437
Review45NANA
Final Examination
* It is a tentative plan and can be changed as per requirement.
 
 
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