Course Overview
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Course Synopsis
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This is a graduate level course. It builds on the concepts presented in the undergraduate computer architecture course. The emphasis is given to expose advances in the field through cost-performance-power trade-offs and good engineering design of computers. The course introduces the quantitative principles of computer design, performance enhancement methodologies, static and dynamic exploitation of instruction level parallelism in high-performance processors and performance enhancement of memory and input/output systems.
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Course Learning Outcomes
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Upon successful completion of this course, students should be able to:
- Understand the quantitative principles of computer design and metrics for performance measurement.
- Familiarize the benchmark to analyze the performance of different architectures.
- Exploit instruction level parallelism using static and dynamic techniques in high-performance processors including superscalar execution.
- Recognize the centralized and distributed share-memory multiprocessor architectures.
- Design memory hierarchy and storage systems with optimum performance.
- Be acquainted to input/output systems design and their performance benchmarks.
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Course Calendar
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1
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History and Introduction
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2
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Quantitative Principles
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3
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Quantitative Principles (Continue)
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4
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Instruction Set Architecture (ISA)
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5
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Instruction Set Architecture (ISA) (Continue)
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6
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Instruction Set Architecture (ISA) (Continue)
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7
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Computer Hardware Design
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8
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Computer Hardware Design (Continue)
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9
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Computer Hardware Design (Continue)
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10
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Computer Hardware Design (Cont.)
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11
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Computer Hardware Design (Cont.)
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13
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Instruction Level Parallelism (ILP) (Continue)
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14
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Instruction Level Parallelism (ILP) Continue.
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15
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Instruction Level Parallelism (ILP) Continue..
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16
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Instruction Level Parallelism (ILP) Continue
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17
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Instruction Level Parallelism (ILP) Continue
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18
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Instruction Level Parallelism (ILP) Continue
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19
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Instruction Level Parallelism (ILP) Continue
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20
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Instruction Level Parallelism (Static Scheduling)
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21
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Instruction Level Parallelism (Static Scheduling - Multiple Issue Processor)
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22
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Instruction Level Parallelism (Software pipelining and Trace Scheduling)
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23
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Instruction Level Parallelism (Hardware Support at Compile Time)
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24
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Instruction Level Parallelism (Concluding Instruction Level Parallelism)
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25
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Memory Hierarchy Design (Storage Technologies Trends and Caching)
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26
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Memory Hierarchy Design (Concept of Caching and Principle of Locality)
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27
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Memory Hierarchy Design(Cache Design Techniques)
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28
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Memory Hierarchy Design(Cache Design and policies )
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29
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Memory Hierarchy Design(Cache Performance Enhancement by(Reducing Cache Miss Penalty):
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30
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Memory Hierarchy Design(Cache Performance Enhancement)(Reducing Miss Rate)
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31
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Memory Hierarchy Design(Cache Performance Enhancement by )(Miss Penalty/Rate Parallelism a
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32
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Memory Hierarchy Design (Main and Virtual Memories)
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33
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Memory Hierarchy Design(Virtual Memory System)
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34
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Multiprocessors(Shared Memory Architectures)
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35
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Multiprocessors(Cache Coherence Problem)
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36
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Multiprocessors(Cache Coherence Problem … Cont’d )
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37
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Multiprocessors(Performance and Synchronization)
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38
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Input Output Systems(Storage and I/O Systems)
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39
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Input Output Systems(Bus Structures Connecting I/O Devices)
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40
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Input Output Systems(RAID and I/O System Design)
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41
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Networks and Clusters (Networks: Interconnection and Topology )
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42
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Networks and Clusters(Networks Topology and Internetworking .. Cont’d)
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43
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Networks and Clusters(Internetworks and Clusters)
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44
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Putting It All Together(Case Studies)
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45
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Putting It All Together(Review: Lecture 1 - 43)
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